Interface-state density of three dimensional silicon channels measured by charge pumping method

Recently, multi-gate and nanowire field-effect-transistors (FETs) with three-dimensional (3D) channels have drawing much interest because they have excellent short-channel-effect immunity due to better electrostatic control of the channel potential by gate electrodes. Therefore, the metal-oxide-semiconductor (MOS) transistor with 3D channels has been considered as one of the promising candidates to overcome the scaling issues in planar FETs. Generally, the 3D channels formed by plasma etching and/or oxidation process are consisted of various crystallographic orientations: facets or rounding shapes. One of the concerns with these structures is the interface-state density (Dit), which is strongly dependent on the surface orientations. Therefore, a direct measurement of cross-sectional-shape dependent Dit and its distribution in energy band gap (Eg) is required. In this study, the interface-state density of 3D Si body with rectangular cross section was measured by charge-pumping method with gated PIN diodes formed on a silicon-on-insulator (SOI) wafer. The PIN diodes were fabricated on line structures (fins) ranging from 70 to 110 nm in width and a (100)-oriented planar SOI layer of 70 nm thick as a control. 14-nm-thick gate-oxide film was formed by dry oxidation at 1000C for 10 min. P and BF2 ions were implanted to form N and P regions, respectively, each adjacent to the gate electrode. A tungsten (W) film was deposited by rf magnetron sputtering, followed by the formation of the gate electrode by wet etching. Then, samples were subjected to the activation annealing in nitrogen gas ambient at 800C for 5 min. Finally, the sample was annealed in forming gas (F.G.) (N2 : H2 = 97 : 3) ambient at 300 to 600C for 30 min. The interface-state density of the planar SOI structure was almost independent on the channel length and width. F.G. annealing temperature dependence was investigated for the 3D Si structures. With increasing the F.G. annealing temperature from 300 to 420C, the interface-state density decreased gradually, especially at near the midgap. Further, with increasing the forming gas annealing temperature from 420 to 540C, the interface-state density, on the contrary, increased gradually. The fin structures had higher Dit value than the planar SOI in the entire energy range in the gap. Moreover, the increase in Dit with decreasing the width of fin structures was found. From the fin-width dependency, Dit values of 1.3 x 10 and 2.6 x 10 cm eV for top and side surfaces were extracted, respectively. It can be modeled that Dit can be estimated by the averaged Dit values of top and sidewall surface areas, in proportion to the channel width. CONTENTS Chapter